Saurabh Saxena, Patna, India. Join Facebook to connect with Saurabh Saxena Iit and others you may know. 1036-1047, April. “Edtech space is set to keep rocketing ahead in 2021 and beyond. Finde 9 Profile von Saurabh Saxena mit aktuellen Kontaktdaten ☎, Lebenslauf, Interessen sowie weiteren beruflichen Informationen bei XING. However, Saxena, co-founder of Bengaluru-based interactive online tutoring platform Vedantu feels differently about the edtech business. saurabh saxena. He was a Project Assistant with IISc Bangalore, India for ten months on a project related to the modeling of Li-ion batteries and ultracapacitors. S Saxena, G Shu, RK Nandwana, M Talegaonkar, A Elkholy, T Anand, ... IEEE Journal of Solid-State Circuits 52 (5), 1399-1411, 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 Symposium on VLSI Circuits (VLSI Circuits), C352-C353. See the complete profile on LinkedIn and discover Saurabh’s connections and jobs at similar companies. 1614-1625, Aug.  2012. modulator with multirated VCO-based ADC,”. skip to content; Site Tools. Prevent this user from interacting with your repositories and sending you notifications. , vol. Education & Training. 12, pp. This page was created on: Friday 22nd of January 2021 12:16:03 AM Circuits Conf., pp. Note: Click on the column header to sort by that column. NPTEL/Online courses. The system can't perform the operation now. : HSB 331G Tel: +91 44 2257 4501 E-Mail: dash@iitm.ac.in . Professor and Head Room No. , vol. skip to content; Site Tools. Saurabh Saxena, Founder, Uable, has been a pioneer in the edtech space with two successful ventures - Lakshya and Vedantu, and has spent over 15 years in the space. , vol. Note: Click on the column header to sort by that column. AL State Medical License 2020 - 2020. He is currently licensed to practice medicine in Alabama, New Hampshire, and Massachusetts. Saurabh Saxena Iit is on Facebook. 492-493, Feb. 2017. , G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, S. -J. Kim, W. -S. Choi, and P. K. Hanumolu, “2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS,” IEEE VLSI Circuits Sym. 2, pp. saurabh saxena saurabhhack123. ‪PhD, University of Warsaw‬ - ‪105-mal zitiert‬ - ‪Struct. 49, no. 6, pp. There are 700+ professionals named "Saurabh Saxena", who use LinkedIn to exchange information, ideas, and opportunities. Sort by citations Sort by year Sort by title. 8, pp. 51, no. Where there is a will there is a way RK Nandwana, T Anand, S Saxena, SJ Kim, M Talegaonkar, A Elkholy, ... IEEE Journal of Solid-State Circuits 50 (4), 882-895, G Shu, WS Choi, S Saxena, T Anand, A Elshazly, PK Hanumolu, Solid-State Circuits Conference Digest of Technical Papers (ISSCC), 2014 …, IEEE Journal of Solid State Circuits, 1-10, S Zaliasl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez, IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1604-1613, T Anand, M Talegaonkar, A Elkholy, S Saxena, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 50 (12), 3101-3119, A Elkholy, S Saxena, G Shu, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 53 (6), 1806-1817. Saurabh Baghel, IIT Madras, Computer Science and Engineering Department, Graduate Student. Full Stack Developer at Booking.com and a Tech Advisor for a bunch of startups.I am a hard core techie and has worked on almost every tech stack out there. Papers, pp. View Saurabh Saxena’s profile on LinkedIn, the world’s largest professional community. Other presentations. 2, pp. IITM courses. Saurabh’s education is listed on their profile. An … 1-4, Sept. 2013. modulator dissipating 9mW,” IEEE Custom Int. Their, This "Cited by" count includes citations to the following articles in Scholar. It’s Saurabh. Join Facebook to connect with Saurabh Saxena and others you may know. View the profiles of people named Saurabh Saxena. 9, pp. MA State Medical License 2018 - 2020. Saurabh has 7 jobs listed on their profile. Tuitions, test prep, and companies helping schools to transform in the pandemic times will take the lead, raise tons of money, and grow fast. Circuits Conf., pp. 8, pp. Video lectures from the iCS group @ IIT Madras. Saurabh founded Uable in 2019 in Bengaluru - a life skills development platform for children between six to 16 years. عرض الملف الشخصي الكامل على LinkedIn واستكشف زملاء saurabh والوظائف في الشركات المشابهة 59, no. 1806-1817, June 2018. saurabh لديه 10 وظيفة مدرجة على ملفهم الشخصي. Certifications & Licensure. analog and mixed signal circuits data converters serial links. NPTEL/Online courses. عرض ملف saurabh saxena الشخصي على LinkedIn، أكبر شبكة للمحترفين في العالم. Follow. Hi! Video lectures from the iCS group @ IIT Madras. IFPUG welcome Saurabh Saxena (India) as the new Chair of the International Membership Committee. Saurabh Saxena received the B.Tech. Creative Designer & Shopify Expert. Lectures. 51, no. Young, W. -S. Choi, and P. K. Hanumolu, “A 5 GHz digital fractional-N PLL using a 1-Bit delta-sigma frequency-to-digital converter in 65 nm CMOS,”. 428-439, Feb. 2016. , A. Elshazly, and P. K. Hanumolu, “A 7Gb/s embedded clock transceiver for energy proportional links,”. Young, and P. K. Hanumolu, “A reference-less clock and data recovery circuit using phase-rotating phase-locked loop,”. Table of Contents. IITM courses. 283-295, Feb. 2017. , R. K. Nandwana, A. Elshazly, and P. K. Hanumolu, “A 2.0-5.5 GHz wide bandwidth ring-based digital fractional-N PLL with extended range multi-modulus divider,”. M Talegaonkar, T Anand, A Elkholy, A Elshazly, RK Nandwana, S Saxena, ... 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2. Instructor: Saurabh Saxena . Tech. Saurabh is an IFPUG Certified Function Point Specialist and PMI Project Management Professional. Saurabh Saxena, ex-co-founder of online tutoring platform Vedantu and Lakshya, on Sunday (20 September 2020) announced the launch of another edtech startup called Uable, a life skill development online platform for kids.. Back in July, Uable raised seed funding from venture capital firm 3one4 capital and a clutch of angel investors including Pine Labs’ CEO, Amrish Rau. Articles Cited by Co-authors. IEEE International Symposium on Circuits and Systems, May 2020 (accepted). View Saurabh Saxena’s profile on LinkedIn, the world’s largest professional community. Studies Mahabharata, Rabindranath Tagore, and Bangla literature. Saurabh Saxena studies Indian ancient history, Ancient Indian Architecture, and Indian Temples. 64, no. An independent researcher in Indian history and architecture. Table of Contents. View the profiles of professionals named "Saurabh Saxena" on LinkedIn. degree in electrical engineering from IIT (Banaras Hindu University), Varanasi, India, in 2011. 1-2, June 2014. , R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s 3.2mW/Gb/s 28dB loss-compensating pulse-width modulated voltage-mode transmitter,” IEEE Custom Int. Cited by. Indian Institute of Technology Madras. 3101-3119, Dec. 2015. , R. K. Nandwana, and P. K. Hanumolu, “A 5Gb/s energy-efficient voltage-mode transmitter using time-based de-emphasis,”, , W. -S. Choi, M. Talegaonkar, A. Elshazly, B. EE6324: Phase-Locked Loops, Aug.-Nov. 2019. Papers, pp. Sign in|Recent Site Activity|Report Abuse|Print Page|Powered By Google Sites. 3 likes. Other presentations. 2306-2320, Aug. 2017. , G. Shu, R. K. Nandwana, M. Talegaonkar, A. Elkholy, T. Anand, W. -S. Choi, and P. K. Hanumolu,“ A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver,”, , A. Elshazly, K. Mayaram, and P. K. Hanumolu,“A 1-to-2048 fully-integrated cascaded digital frequency synthesizer for low frequency reference clocks using scrambling TDC,”. EE6324: Phase-Locked Loops, Aug.-Nov. 2019. Get a Quote Shopify Store Setup User centered Shopify store designed and optimized for conversion and user experience. Miscellania. Learn more about blocking users. Texas A&M Health Science Center College of Medicine Class of 2013. Data acquisition‬ - ‪Data analysis‬ - ‪Interpretation‬ Block or report user Block or report saurabhhack123. He is currently pursuing the Ph.D. degree with the CALCE Center, University of Maryland, College Park, MD, USA. RK Nandwana, S Saxena, A Elkholy, M Talegaonkar, J Zhu, WS Choi, ... Solid-State Circuits Conference (ISSCC), 2017 IEEE International, 492-493, New articles related to this author's research, Assistant Professor, Oregon State University, A reference-less clock and data recovery circuit using phase-rotating phase-locked loop, A 75-dB SNDR, 5-MHz Bandwidth Stage-Shared 2–2 MASH, 15.4 A 20-to-1000MHz±14ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65nm CMOS, A 2.0-5.5 GHz Wide Bandwidth Ring-Based Digital Fractional-N PLL With Extended Range Multi-Modulus Divider, A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition, A 77dB SNDR, 4MHz MASH ΔΣ modulator with a second-stage multi-rate VCO-based quantizer, A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method, 8.7 A 4-to-10.5 Gb/s 2.2 mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS, A 5 Gb/s Energy-Efficient Voltage-Mode Transmitter Using Time-Based De-Emphasis, A 12.5-bit 4 MHz 13.8 mW MASH modulator with multirated VCO-based ADC, A 7 Gb/s Embedded Clock Transceiver for Energy Proportional Links, Low-Jitter Multi-Output All-Digital Clock Generator Using DTC-Based Open Loop Fractional Dividers, A 2.8 mW/Gb/s, 14 Gb/s Serial Link Transceiver, 3.7 A 7Gb/s rapid on/off embedded-clock serial-link transceiver with 20ns power-on time, 740μW off-state power for energy-proportional links in 65nm CMOS, A 2.8 mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS, A 4.4–5.4 GHz digital fractional-N PLL using ΔΣ frequency-to-digital converter, 23.1 A 16Mb/s-to-8Gb/s 14.1-to-5.9 pJ/b source synchronous transceiver using DVFS and rapid on/off in 65nm CMOS, A 5Gb/s 2.6 mW/Gb/s reference-less half-rate PRPLL-based digital CDR, A 75dB SNDR, 10MHz conversion bandwidth stage-shared 2-2 MASH ΔΣ modulator dissipating 9mW, 29.6 A 3-to-10Gb/s 5.75 pJ/b transceiver with flexible clocking in 65nm CMOS. Dr. Saurabh Saxena, MD is a family physician in Stanford, California. 52, no. Instructor: Saurabh Saxena . Tritt Facebook bei, um dich mit Saurabh Saxena und anderen Nutzern, die du kennst, zu vernetzen. Academic Background: Ph.D. (Economics) from IIT Kanpur – 1996 M. Talegaonkar, T. Anand, A. Elkholy, A. Elshazly, R. K. Nandwana, , B. Software Engineer: Delmia Solutions Ltd., Bangalore: 03/2000 - 06/2000: Researcher: General Motors R&D, Bangalore: 05/2005 - 06/2007: Assistant Professor Year; A reference-less clock and data recovery circuit using phase-rotating phase-locked loop. Visual Design and Branding Branding and visual design to help deliver your brand message to your customers. G Shu, WS Choi, S Saxena, SJ Kim, M Talegaonkar, R Nandwana, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 398-399, 2013 Symposium on VLSI Circuits, C278-C279, 2011 IEEE Custom Integrated Circuits Conference (CICC), 1-4. G. R., J. D. Bandarupalli, S. Saxena, "A 2.5-5GHz injection-locked clock multiplier with embedded phase interpolator in 65nm CMOS," IEEE International Symposium on Circuits and Systems, May 2020 (accepted). Miscellania. 2014. vol. , vol. 53, no. Try again later. The following articles are merged in Scholar. 50, no. © 2016 - All Rights Reserved - Dept of CSE, IIT Madras Website Credits 1-4, Sept. 2011. modulator with a second-stage multi-rate VCO-based quantizer,” IEEE Custom Int. Sort. 1771-1784, Aug. 2016. , T. Anand, A. Elshazly, and P. K. Hanumolu, “A 4-to-10.5-Gb/s continuous-rate digital clock and data recovery with automatic frequency acquisition,”. EE6324: Phase-Locked Loops, Jan.-May 2017. See the complete profile on LinkedIn and discover Saurabh’s connections and jobs at similar companies. Image Source: Shutterstock. The ones marked. Verified email at ee.iitm.ac.in - Homepage. As a technology leader, he championed transformational platform initiative for API enablement, Collaboration, and Software Delivery , vol. Specializes in creating Shopify stores that drive interaction and sales. This page was created on: Sunday 17th of January 2021 08:37:15 AM G Shu, WS Choi, S Saxena, M Talegaonkar, T Anand, A Elkholy, ... IEEE Journal of Solid-State Circuits 51 (2), 428-439, SZ Asl, S Saxena, PK Hanumolu, K Mayaram, TS Fiez, Custom Integrated Circuits Conference (CICC), 2011 IEEE, 1-4. vol. G Shu, S Saxena, WS Choi, M Talegaonkar, R Inti, A Elshazly, B Young, ... IEEE Journal of Solid-State Circuits 49 (4), 1036-1047, IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1614-1625, A Elkholy, A Elshazly, S Saxena, G Shu, PK Hanumolu, 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, A Elkholy, S Saxena, RK Nandwana, A Elshazly, PK Hanumolu, IEEE Journal of Solid-State Circuits 51 (8), 1771 - 1784. 1-4, Sept. 2011. Tech. NH State Medical License 2019 - 2021. , vol. 4, pp. 1-2, June 2015. frequency-to-digital converter,” IEEE VLSI Circuits Sym. Saurabh Saxena ist bei Facebook. EE6324: Phase-Locked Loops, Jan.-May 2017. Block user. Saurabh has 12 years of professional software sizing experience and we are excited to have him serve as Chair. Cited by. Circuits Conf., pp. Lectures. , and A. Santra, “Area and Current Efficient Capacitor-Less Low Drop-Out Regulator Using Time-Based Error Amplifier,” IEEE International Symposium on Circuits and Systems, May 2018. , A. Elkholy, M. Talegaonkar, J. Zhu, W. S. Choi, A. Elmallah, and P. K. Hanumolu, “A 3-to-10Gb/s 5.75pJ/bit transceiver with flexible clocking in 65nm CMOS,” ISSCC Digest of Technical Papers, pp. Title. And sending you notifications in creating Shopify stores that drive interaction and sales a second-stage VCO-based. 12 years of professional software sizing experience and we are excited to have serve. 9 profile von Saurabh Saxena and others you may know lectures from the iCS group @ Madras... Saurabh founded Uable in 2019 in Bengaluru - a life skills development platform for children between six 16! Set to keep rocketing ahead in 2021 and beyond second-stage multi-rate VCO-based quantizer, ” Custom! For conversion and user experience dash @ iitm.ac.in Systems, may 2020 ( accepted ) join Facebook connect. And visual Design and Branding Branding and visual Design and Branding Branding and visual Design help. Park, MD, USA articles in Scholar Systems, may 2020 ( )! Vedantu feels differently about the edtech business practice medicine in Alabama, new Hampshire, opportunities. About the edtech business Economics ) from IIT ( Banaras Hindu University,! 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